Data Flow, Synchronization, and Latency Explained

Overview of data flow, time synchronization, and latency in mixed-signal, multichannel Q.series data acquisition systems.

Understanding the Importance of Data Synchronization

In test and measurement technology, synchronization refers to the precise alignment of processes in time. A lack of synchronization can lead to several issues, including:

Misalignment or drift between data recorded by different measurement devices
Inconsistent measurement start times across devices
Inaccurate analysis results, as many methods rely on precise time correlation

Ensuring proper synchronization is essential for reliable, high-quality measurement and analysis. The Q.series data acquisition system is designed for synchronized measurement and data processing in mixed-signal, multichannel, and distributed setups. Ensuring that all analog-to-digital converters (ADCs) measure simultaneously is critical for maintaining data integrity and timing accuracy.

Data Flow Architecture

At the core of the Q.series DAQ system is the Q.station controller, a central processor that ensures synchronized measurements across all channels. In addition to synchronization, the Q.station features circular buffers optimized for high-speed data streaming and supports intelligent protocol conversion.

The block diagram below illustrates the data flow from the UART interfaces on the right, where the DAQ modules are connected, to the data clients on the left.

FPGA-Driven Synchronization and Timestamping

The Q.station controller communicates with DAQ modules using Gantner Instrument’ proprietary Localbus protocol over RS-485. Each analog input module features dedicated ADCs per channel, all driven by a common sync pulse issued by the controller’s FPGA. This sync pulse not only initiates simultaneous sampling across all channels but also aligns the internal clocks of the ADCs across modules, ensuring they operate in phase. As a result, all analog inputs are sampled at the exact same instant.

The Q.station is equipped with four UARTs (Universal Asynchronous Receiver-Transmitters) for high-speed serial communication. A central FPGA coordinates these UARTs, triggering the sync pulse on all four interfaces simultaneously to maintain precise synchronization.

Timestamping is also handled by the FPGA, enabling high-precision timing with jitter under 100 ns. The timestamp corresponds to the moment the sync pulse is issued, ensuring accurate temporal alignment with the sampled data.

The FPGA processing loop, which handles tasks such as data collection, formatting, and buffering, requires 1 to 3 iterations per cycle, depending on system load and performance requirements. The maximum FPGA loop rate, also referred to as the system sample rate, is 100 kHz.

Configurable Controller Clock Synchronization

The controller time can be set manually, synchronized with another controller in multi-controller DAQ systems, or aligned with an external time source.

Data Buffering for Different Sampling Rates

The Q.station controller supports up to four different sample rates, optimizing both memory usage and network throughput. This approach ensures that low-frequency measurement data is not transmitted through the system at the same rate as high-speed data in mixed-signal applications.

For each sample rate, a separate circular buffer (or ring buffer) is allocated in the CPU memory. Sample rate #1 corresponds to the system sample rate, while sample rates #2, #3, and #4 are divisors of the system sample rate. Data samples from the FPGA buffers are sent to the circular buffers at a fixed rate of 10 kHz, with oversampling applied when necessary. The samples that share the same timestamp are grouped together into unique datasets.

It is possible to configure variables with different sample rates on a single UART. The UART will then sample the bus at the frequency of the variable with the highest sample rate. This configuration ensures that there is no data skew between variables, even if they have different sample rates.

Efficient Data Streaming over TCP/IP

Data from each circular buffer is streamed separately to data clients (such as GI.bench or third-party applications) via TCP/IP. The high-throughput stream processor uses shared memory with multiple access points to prevent redundant data transfer, optimizing performance. The stream processor runs in the non-real-time part of the CPU and can process data at up to 100 kHz asynchronously. The refresh rate (also known as the handling interval) for data clients is user-configurable, with a minimum interval of 100 ms (10 Hz).

Combining Multiple Data Streams

GI.bench provides the ability to merge multiple data streams into a single stream. This feature offers benefits such as writing all data into a single log file without needing to manually merge the data. GI.bench uses the timestamp from one data stream to align with the closest timestamp in other data stream(s). For accurate upsampling or downsampling, the resulting sample rate of the merged data stream must be a direct divisor of the source sample rates.

The video tutorial below explains the data stream merging feature in GI.bench:

Synchronization Error and Signal Propagation Delay

In principle, the measurement error due to synchronization between channels connected to a single controller is negligible. However, when different types of signal conditioning filters are used between channels, a propagation delay may be introduced. In such cases, a signal propagation delay of 100 μs should be considered when calculating the measurement error.

In a multi-controller system, the time synchronization error between controllers must also be accounted for. Please refer to the section on Q.station clock synchronization for more details.

Calculating Total System Latency

The overall latency can be calculated by adding the latency in the FPGA, the transfer rate to the circular buffer, and the data stream handling interval.

Latency [s] = 3 / system sample rate [Hz] + 0.0001 [s] + data stream handling interval [s]

Example:

For a controller running at 10 kHz with a 10 Hz data stream update rate, the latency is:
3 / 10'000 + 0.0001 + 0.1 = 0.1004 seconds.