Data Flow, Synchronization, and Latency

Overview of data flow, time synchronization, and latency in mixed-signal, multichannel Q.series data acquisition systems

The importance of data synchronization

In test and measurement technology, the term synchronization refers to the alignment of processes in terms of time. Problems that can occur when there is a lack of synchronization include:

Data recorded by different measuring devices not aligning or even drifting apart.
The start of the measurement not taking place at the same time for different devices.
Many analysis methods requiring accurate time measurement. If the time measurement is inaccurate due to a lack of synchronization, this can lead to erroneous analysis results.

The Q.series data acquisition system has been designed for synchronized measurement and data processing in mixed-signal, multichannel, and distributed configurations. It is of paramount importance for all analog-to-digital converters (ADCs) in a Q.series data acquisition system to measure at the same time.

Data flow

The beating heart of the Q.series DAQ system is its central processor, called Q.station. The Q.station not only ensures synchronized measurement for all channels, but it also comes with circular buffers optimized for data streaming and intelligent protocol conversion. The block diagram below shows the data flow from the UARTs on the right (where the I/O modules are connected) to the data clients on the left.

Analog input measurement

A Q.station controller communicates with the I/O modules via the proprietary Localbus protocol over RS-485. The analog input modules come with separate ADCs per channel that are driven with a single sync pulse command coming from the controller's FPGA. The sync pulse is also used to align the ADC clocks across all modules to ensure they are all running in phase. The result is that all analog inputs are sampled at the same instant.

Each Q.station controller comes with 4 UARTs (Universal Asynchronous Receive-Transmitters) for transmitting and receiving serial data. A high-speed FPGA inside the Q.station controller ensures that the sync pulse is triggered on all 4 UARTs at the same instant.

Timestamping is done in the FPGA to ensure the highest performance with minimal jitter (<100 ns). To ensure that the timestamp matches the time of the sample taken by the ADC, the FPGA uses the time when the sync pulse command was given to calculate the exact timestamp.

The number of iterations required by the FPGA to process the data samples varies between 1 - 3 iterations depending on available performance. The maximum FPGA loop rate, also known as the system sample rate, is 100 kHz.

Q.station clock synchronization (optional)

The controller time can be set manually, synchronized to another controller (for multi-controller DAQ systems), or synchronized to an external time source.

Data buffering with different sampling rates

The Q.station controller supports up to 4 different sample rates for optimizing memory usage and network throughput. This avoids that for mixed-signal data acquisition low-frequency measurement data is transmitted through the system at the same frequency as high-speed measurement data.

For each sample rate, a separate circular buffer (also known as ring buffer) is created in the CPU memory. Sample rate 1 is identical to the system sample rate. Sample rates 2, 3, and 4 can be a straight divider of the system sample rate. Data samples from the FPGA buffers are sent to the circular buffers at a fixed rate of 10 kHz using oversampling where needed. The individual data samples that share the same timestamp are then grouped into unique datasets.

It is possible to configure variables with different sample rates on one UART. The UART will then sample the bus at the frequency of the variable with the highest sample rate. It is ensured that there is no data skew between variables with different sample rates.

Data streaming over TCP/IP

Data from each circular buffer is streamed separately to the data consumers (GI.bench or third-party application) via TCP/IP. The high-throughput stream processor is based on shared memory with multiple access points to avoid redundant data transfer to optimize performance. The stream processor runs in the nonreal-time part of the CPU and can process 100 kHz data asynchronously. The refresh rate (also known as handling interval) for the data consumers is user-configurable with a minimal interval of 100 ms (10 Hz).

Merging data streams

GI.bench offers the functionality to merge multiple data streams into one stream on the host application. Benefits could be for example to write all data into one log file without the need to merge data manually. To merge data it uses the timestamp in one data stream to match the closest timestamp in the other data stream(s). For correct up or downsampling, the resulting sample rate of the merged data stream can only be a straight divider of the source sample rates.

The video tutorial below explains the data streaming merging feature in GI.bench:

Overall synchronization accuracy

In principle, the measurement error due to synchronization between channels connected to one controller is neglectable. When using different types of signal conditioning filters between the channels, a propagation delay may be introduced. In that case, a signal propagation delay of 100 μs should be taken into account for calculating the measurement error.

In a multi-controller system, the time synchronization error between controllers needs to be taken into account as well. See the section about Q.station clock synchronization.

Overall latency

The overall latency can be calculated by adding the latency in the FPGA, the transfer rate to the circular buffer, and the data stream handling interval:

👉 Latency [s] = 3 / system sample rate [Hz] + 0.0001 s + data stream handling interval [s]

Example:
For a controller running at 10 kHz with a 10 Hz data stream update rate, the latency is:
3/10000 + 0.0001 + 0.1 = 0.1004 seconds.