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      Arithmetic functions: standard vs. signal conditioning

      The Q.series X I/O modules separate between standard arithmetic functions and signal conditioning arithmetic functions. Why is this?

      For Q.series X I/O modules, the same functions (e.g., selRMS, max, or min) can be configured either as standard arithmetic or as signal conditioning arithmetic variables.

      The key difference lies in where these calculations are performed. Standard arithmetic variables are processed in the DSP (Digital Signal Processor), whereas signal conditioning arithmetic variables are calculated directly in the FPGA (Field-Programmable Gate Array). Standard arithmetic functions derive their results from values read by the DSP from the FPGA, whereas signal conditioning functions work directly with raw or processed signals inside the FPGA.

       

      Standard arithmetic functions

      These functions are computed in the DSP and are affected by CPU load, which can impact their speed and performance.

      • -
      • +
      • *
      • /
      • min()
      • max()
      • selRMS(Vx; Ts) ... Ts = integration time (period of the processed signal)
      • integ()
      • spec1()
      • spec2()
      • spec3()
      • spec4()
       

      Signal conditioning arithmetic functions

      These functions operate inside the FPGA, leveraging direct processing at the module's sample rate for faster and more precise calculations.

      • min() … min value of an analog or remote input
      • max() … max value of an analog or remote input
      • selunb() … analog input unbalanced value (Raw)
      • selgro() … gross value Gro = Raw - null
      • selnet() … netto value Netto = Gro - tare
      • selRMS(Vx; Ts) … Ts LP rise time (should be several periods of the processed signal)
      • selmul() … multiplies 2 following analog input channels (Ain0*Ain1, Ain1*Ain2, …)
      • spec1()
      • spec2()
      • spec3()
      • spec4()
      For more information on the individual functions, useful details can be found in the software by pressing the question mark.
       
      Signal Conditioning 2

      Processing Differences: DSP vs. FPGA

      The performance and precision of these calculations depend on whether they are executed in the DSP or the FPGA:

      • DSP-based calculations: Execution speed depends on CPU load. When CPU load is high, calculation performance might degrade.

      • FPGA-based calculations: These run in direct relation to the module's configured sample rate, providing higher precision and faster results without CPU load constraints.

      Example: RMS Calculation Comparison

      Below is an example demonstrating the difference between DSP-based arithmetic and FPGA-based signal conditioning using RMS calculations. The YT-chart screenshot highlights the contrast:

      • Blue Line: RMS calculation via DSP-based arithmetic

      • Red Line: RMS calculation via FPGA-based signal conditioning

      The signal conditioning RMS calculation shows significantly more data points and provides a more accurate result compared to the DProcessing Differences: DSP vs. FPGA

       

      Signal Conditioning


      Supported Arithmetic and Signal Conditioning Functions Across Modules

      Not all functions are available on every module. The availability of arithmetic and signal conditioning functions depends on the specific Q.series X module used. Modules vary in terms of:

      • Maximum number of channels per module

      • Transfer rate limitations via UART or other communication interfaces

      • Available FPGA processing resources