Firmware Description for the Prototype A152

Wiring: The behavior of the module regarding the zero signal:
- 2-wire: Z-track is ignored.
- 3-wire: Z-track resets the counter to zero on every pass.
- 4-wire: Z-track resets the counter to zero only on the first pass.
Scaling:
- Minimum value
- Maximum value
Edges per Revolution: This is used to mask the value range of the counted edges at $0 \dots 360^{\circ}$, ensuring there are no negative values.
- Positive direction of rotation: 0, 1, ... 360, 0, 1, 2 ...
- Negative direction of rotation: 0, 360, 359, ... 1, 0, 360 ...
Signal Amplitude: Used to adjust the chip's gain in the future, currently this parameter has no influence
Filtering: Not yet implemented, if necessary the sample rate a.s.o. have to be specified

The values read from the chip NQE EVAL NQ8D by the FPGA and the calculated results can be retrieved and transmitted on the bus as follows.

Integer values, unscaled.

The values $x$ from the list above are scaled using a factor and an offset.

Up to 8 calculation channels can be defined this way.
"x" corresponds to the entries in the spec1(x) list.
The values ActualPosition_Old and RelPosition_Old are stored during each calculation cycle and used in the following cycle.
Currently, calculations are performed at 100 µs, 10 kSPS
The calculation time, cycle can be increased by the SDO 800A:05 Downsample
- 0, 1 ... the differences are calculted ever sample 10kSPS
- 2 ... the calculations are done every 5kSPS
- 3 ... the calculations are done every 3.3kSPS
- 4 ... the calculations are done every 2.5kSPS
- a.s.o.